Certain radio frequency transmission modules are adapted to obtain a signal at a first frequency F1 carrying the desired information, and to convert this signal to a radio frequency carrier of frequency FLO for its radio transmission by antenna. The desired information is then in fact carried by a second radio frequency F1+FLO. The frequency F1 can be the zero frequency (baseband) or a frequency called an “intermediate frequency.”
It is known that the conversion to the second frequency generates a desired signal at the second frequency F1+FLO, a signal corresponding to the carrier at frequency FLO and an image signal at the frequency F1−FLO.
There are generally set constraints regarding such a radio frequency transmission module. These constraints include, for example, a maximum limit for the ratio of the image signal level to the desired signal level, called the image rejection ratio (IRR).
Let us consider a radio frequency transmission module 110 such as the one represented in FIG. 1. It comprises, for example, a digital signal processor (DSP) 100 adapted to deliver a digital signal of frequency F1 on an I channel (in-phase channel), and a digital signal of frequency F1 on a Q channel (quadrature channel).
Each of these signals is input to a respective digital-to-analog converter (DAC) 101, 102 and the analog signals output by the digital-to-analog converters are input to a conversion stage 103 for conversion to a radio frequency F1+FLO.
The frequency conversion stage 103 comprises two mixers 112, 114, using a Gilbert structure for example.
The mixer 112 placed on the I channel is adapted to mix the signal on the I channel provided as input to the conversion stage 103, for conversion to a signal with a carrier signal LO at radio frequency FLO.
The mixer 114 placed on the Q channel is adapted to mix the signal on the Q channel provided as input to the conversion stage 103, for conversion to a signal with a carrier signal LO′ at radio frequency FLO, and out of phase by 90°relative to the carrier signal LO.
In an operational phase, the signals resulting from this mixing and issuing from the I and Q channels are summed, then delivered by the conversion stage 103 before any further processing is applied to them, then sent to a power amplifier 104. It is then transmitted by a transmitting antenna.
In a calibration phase, test digital signals, in the shape of a sine or cosine wave for example, are delivered by the digital signal processor 100 on the I and Q channels. The signal provided by the power amplifier 104 is then input to a calibration loop 105.
The calibration loop 105 comprises a power detector 106, an analog-to-digital converter (ADC) 107, and a digital signal processor 108.
The power detector 106 is adapted to determine the envelope of the signal provided as input, to detect the power level of said signal, and to determine the IRR corresponding to said signal. The digital signal processor 108 is adapted, if the calculated IRR exceeds the maximum limit set for the IRR, to determine the calibration coefficients as a function of the signal which is provided as input. These determined calibration coefficients are provided as input parameters to the digital signal processor 100.
In the operational phase, the digital signal processor 100 is adapted to process the digital signals (which are no longer test signals) before they are provided to the I and Q channels. This processing can adapt the amplitude and/or phase of the signal intended for the I channel and/or the signal intended for the Q channel as a function of the calibration coefficients determined during the calibration phase and provided as input to the digital signal processor 100.
Thus, the calibration described here enables the IRR value for the desired signals transmitted during the operational phase to be less than the maximum limit tolerated. Note that other calibrations can be performed, with advantages other than image frequency rejection, for example to compensate for non-linearities of the power amplifier.
Such a calibration technique, based on detecting the power level of a signal output by the frequency conversion stage, yields satisfactory results in a certain number of applications. However, it is no longer satisfactory when the maximum limit to be taken into account for the IRR is less than or equal to −40 dB, because it no longer allows sufficient precision.